In most current system architectures, a central processing unit (CPU) has input/output (I/O) devices connected to it via an I/O expansion bus, such as a Peripheral Component Interconnect (PCI) bus. When these devices have something to which they need the CPU to attend, they generate an interrupt. The interrupt causes the CPU to execute a set of code typically called an interrupt handler. The interrupt handler determines the occurrence for which the CPU is needed, clears or acknowledges the interrupt, and then returns the CPU to its usual processing.
Events that may cause an interrupt to be generated can range from normal events like completion of data transfers to or from memory to exceptional events like an error of some kind. Typically, when an event occurs these devices interrupt the CPU and then the CPU determines the occurrence by accessing an interrupt status register (ISR) across the expansion bus. This across-bus accessing can take a microsecond or more depending on the speed of the I/O expansion bus and the devices used to connect to the bus. As CPUs gain in speed, they can perform more instruction cycles per second. Wasting a microsecond in turn wastes more instruction cycles. For example, a 1000 MHz system performs 109 cycles per second, so a 1 microsecond (10−6) stall wastes 1000 (103) cycles. This type of delay begins to impact system performance.